The present disclosure relates to a variable gain amplifier, and more particularly to a technology of correcting a DC offset voltage generated by a variable gain amplifier.
A variable gain amplifier capable of gain control has generally been used in a wireless receiving device. It has been known that a DC (Direct Current) offset voltage causing characteristic deterioration occurs in the variable gain amplifier. This DC offset voltage mainly may occur due to a mismatch of the size or the like of a transistor differential pair in an op amplifier.
A semiconductor integrated circuit related to a technology of correcting (attenuating) the DC offset voltage and disclosed in Japanese Unexamined Patent Application Publication Laid-Open No. 2012-156936 (Patent Document 1) adopts a configuration in which an analog current is applied from a digital-analog converter DAC0 to a caribration resistor R22 and a DC offset voltage in a FILTER 300 is reduced by its voltage drop.
Further, Japanese Unexamined Patent Application Publication Laid-Open No. 2012-099873 (Patent Document 2) has disclosed a configuration in which a DC offset cancel circuit 51 is provided at an output stage of a differential amplifier 5 to reduce an output DC offset voltage. More specifically, the DC offset cancel circuit 51 separates a DC component from a differential output signal of an Amp2 by use of a filter 511 and applies a correction current corresponding to the DC component to an Amp1.